1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to the fabrication of highly sophisticated field effect transistors, such as MOS transistor structures, requiring highly doped shallow junctions.
2. Description of the Related Art
The manufacturing process for integrated circuits continues to improve in several ways, driven by the ongoing efforts to scale down the feature sizes of the individual circuit elements. Presently and in the foreseeable future, the majority of integrated circuits are, and will be, based on silicon devices, due to the high availability of silicon substrates and due to the well-established process technology that has been developed over the past decades. A key issue in developing integrated circuits of increased packing density and enhanced performance is the scaling of transistor elements, such as MOS transistor elements, to provide the great number of transistor elements that may be necessary for producing modern CPUs and memory devices. One important aspect in manufacturing field effect transistors having reduced dimensions is the reduction of the length of the gate electrode that controls the formation of a conductive channel separating the source and drain regions of the transistor. The source and drain regions of the transistor element are conductive semiconductor regions including dopants of an inverse conductivity type compared to the dopants in the surrounding crystalline active region, e.g., a substrate or a well region.
Although the reduction of the gate length is necessary for obtaining smaller and faster transistor elements, it turns out, however, that a plurality of issues are additionally involved to maintain proper transistor performance for a reduced gate length. One challenging task in this respect is the provision of shallow junction regions, i.e., source and drain regions, which nevertheless exhibit a high conductivity so as to minimize the resistivity in conducting charge carriers from the channel to a respective contact area of the drain and source regions. The requirement for shallow junctions having a high conductivity is commonly met by performing an ion implantation sequence so as to obtain a high dopant concentration having a profile that varies laterally and in depth. The introduction of a high dose of dopants into a crystalline substrate area, however, generates heavy damage in the crystal structure and, therefore, one or more anneal cycles are required for activating the dopants, i.e., for placing the dopants at crystal sites, and to cure the heavy crystal damage. However, the electrically effective dopant concentration is limited by the ability of the anneal cycles to electrically activate the dopants. This ability in turn is limited by the solid solubility of the dopants in the silicon crystal. Moreover, besides the dopant activation and the curing of crystal damage, dopant diffusion may also occur during the annealing, which may lead to a loss of dopant atoms in the extension regions, thereby “blurring” the dopant profile. With reference to FIGS. 1a-1c, a typical conventional process flow for forming a conventional field effect transistor will now be described in order to explain the problems involved in more detail.
FIG. 1a schematically shows a cross-sectional view of a transistor structure 100 at an intermediate manufacturing stage. The transistor structure 100 comprises a substrate 101, typically a silicon substrate or a substrate including a silicon layer, in which an active region 103 may be defined by an isolation structure (not shown), such as a shallow trench isolation (STI). A gate electrode 105 is formed above the active region 103 and is separated therefrom by a gate insulation layer 106. A first spacer structure 102 is formed on sidewalls of the gate electrode 105 to provide a desired offset during an implantation process 107 for defining source and drain extension regions 108 in the active region 103. It should be noted that the previously mentioned gate length is, in FIG. 1a, the lateral dimension of the gate electrode 105. The portion of the active region 103 underlying the gate insulation layer 106 represents a channel region 104 disposed between the source and drain extension regions 108.
A typical process flow for forming the transistor structure 100 as shown in FIG. 1a may comprise the following process steps. After formation of isolation structures by sophisticated photolithography, etch and deposition methods, an implantation sequence may be performed to generate a required dopant profile (not shown) within the active region 103. Thereafter, the gate insulation layer 106 is formed by advanced oxidation and/or deposition techniques with a required thickness that is adapted to the gate length of the gate electrode 105. Then, the gate electrode 105 is patterned from an appropriate material, such as polysilicon, by means of advanced photolithography and etch techniques. Next, the ion implantation process 107 may be performed to introduce dopants of a required conductivity type into the active region 103 to thereby form the extension regions 108. If the transistor structure 100 represents a P-channel transistor, a P-type dopant, such as boron, may be used. As previously noted, scaling the gate length of the gate electrode 105 also requires the extension regions 108 to be provided as shallow doped regions with a depth, indicated as 109, in the range of approximately 8-50 nm for a gate length in the range of approximately 30-100 nm. Thus, the ion implantation process 107 is performed with relatively low energy, depending on the type of dopants used, and with a moderately high dose to provide the required high dopant concentration within the extension regions 108.
FIG. 1b schematically shows the transistor structure 100 in an advanced manufacturing stage. A second sidewall spacer structure 110 is provided adjacent to the first spacer structure 102, which may typically be formed of a silicon dioxide liner 110B and a silicon nitride spacer 110A. The spacer structure 110 may be formed by self-aligned deposition and anisotropic etch techniques in order to act as an implantation mask for a subsequent ion implantation sequence 112 to form source and drain regions 111. The overall transistor performance may be affected by the spacer structures 102 and 110, since the relative permittivity of the dielectric material positioned close to the gate electrode 105 and close to the extension regions 108 may have an influence on the degree of charge carrier accumulation within the extension regions 108 due to the capacitive coupling to the gate electrode 105. Hence, it is advantageous to form a significant portion of the spacer structures 110 and 102, for instance the spacers 110A, of silicon nitride, which has a higher dielectric constant compared to silicon dioxide, which thus serve as an efficient etch stop layer during the patterning of the respective silicon nitride layer.
As previously noted, a high dopant concentration is required in the source and drain regions 111 as well as in the extension regions 108 so that severe crystal damage is generated during the implantation sequences 107, 112. Therefore, generally a heat treatment such as a rapid thermal anneal is required, on the one hand, to activate the dopant atoms and to substantially re-crystallize the damaged structure in the source and drain regions 111 and the extension regions 108. During the heat treatment and possibly during other treatments at elevated temperatures in later manufacturing stages, the dopants, and in particular boron, may readily diffuse, thereby compromising the transistor performance due to a loss of dopant atoms in sensitive device areas, such as the extension regions 108. On the other hand, efficiently re-establishing the crystalline structure within the source and drain regions 111 and the extension regions 108 may require relatively high temperatures over a sufficiently long time period, which may, however, unduly increase the dopant diffusion. Especially as device dimensions are scaled to a gate length of 60 nm and even less, the issue of degraded transistor performance, due to a reduced conductivity owing to insufficiently activated dopants and/or a dopant profile blurred by diffusion, is even more important.
FIG. 1c schematically shows the transistor structure 100 after completion of the manufacturing process. Metal silicide regions 115 are formed on top of the gate electrode 105 and the drain and source regions 111, which may comprise nickel, cobalt, tungsten, platinum and the like, or any other appropriate refractory metal. Contact plugs 113 are formed in contact with the drain and source regions 111 to provide electrical contact to further circuit elements (not shown) or other interconnect lines (not shown). The contact plugs 113 may typically be comprised of tungsten and other appropriate barrier and adhesion materials.
Forming the metal silicide regions 115 may typically comprise depositing an appropriate refractory metal and subsequently performing a suitably designed anneal cycle to obtain the metal silicide regions 115 having a significantly lower sheet resistance compared to silicon, even when heavily doped. The contact plugs 113 may be formed by depositing a dielectric material 116, such as silicon dioxide in combination with silicon nitride, and patterning the same to form vias that are subsequently filled with a metal, wherein typically a thin barrier and adhesion layer is formed prior to filling in the bulk metal.
During operation of the transistor structure 100, a voltage may be applied to the contact plugs 113 and a corresponding control voltage to the gate electrode 105 so that, in the case of a P-channel transistor, a thin channel forms in the channel region 104 substantially comprised of holes, indicated by 114, wherein as previously noted the transistor performance, among others, significantly depends on the transition resistance from the channel 104 to the extension regions 108 and from the sheet resistance in the regions 108, since substantially no highly conductive metal silicide is formed in this area. Owing to the complex manufacturing process for forming the extension regions 108 and the drain and source regions 111, i.e., insufficiently cured lattice damage and restricted concentration of activated dopants, in combination with a loss of dopants caused by dopant diffusion, particularly of a readily diffusing species, such as boron, the device performance may be degraded, especially for extremely scaled transistor elements 100, thereby partially offsetting the advantages that are generally obtained by scaling the circuit elements of an integrated circuit.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.